An Ultra-Low Power Fast Transient LDO with Dynamic Bias

A low-dropout linear regulator (LDO) without external capacitors is designed, combining ultra-low power consumption and ultra-fast transient response. The common support voltage of the LDO 2.5 V to 3.6 with a stable output 1.2 an current dynamic range 10 μA 20 mA supply other circuit modules. Rail-to-Rail Input-Output (RRIO) Class AB push-pull amplifier bias are also designed. Meanwhile, which can regulate operating error proposed by monitoring variation in order provide larger compensation operational when load changes at high frequency maintain low clock frequency. designed resistors, deep well NMOS applied stage reduce difficulty loop compensation. Designed 180 nm CMOS process, post-simulation results show that under condition 40 °C 3 input voltage, static 31.7 nA settling time (±5%) less than 35 ns.